Recently, in a semiconductor device (hereinafter, called an LSI (Large Scale Integration)), a plurality of processors has been formed and arranged as a multi-core. For example, in an LSI 1 illustrated in FIG. 1, a plurality of processors are arranged as a core 0, a core 1, a core 2, a core 3, . . . and a power supply voltage VDD and a ground voltage VSS are applied to the core 0, the core 1, the core 2, the core 3, . . . as an internal power voltage ivdd(V) and an internal ground ivss(V) connected through an inductance Ldd(H) and an inductance Lss(H). Also, the internal power voltage is fluctuated since a power current I(A) flows through their inductances when the core 0, the core 1, the core 2, the core 3, . . . operate. An internal power capacitor C(F) is inserted in order to suppress its voltage fluctuation.
While increasing the number of processors being arranged, a scale of power consumed in the LSI tends to be larger. On the other hand, it has been requested to reduce power consumption. In addition to a configuration of the LSI 1 illustrated in FIG. 1, an LSI 1a illustrated in FIG. 2 is configured so that operations of the core 0, the core 1, the core 2, the core 3, . . . are controlled in response to ON and OFF of an operation enable signals en0, en1, en2, en3, . . . by synchronizing with a system clock sclk. This configuration realized to suspend a circuit with respect to each of the core 0, the core 1, the core 2, the core 3, . . . .
However, in response to a request of reducing the power consumption, it is desired to increase frequency of switching an operation of each core in a circumstance of configuring a multi-core and under an operation control of each core. A difference between the power consumptions when the LSI is operating and when the LSI is suspending becomes bigger, and the power supply voltage in the LSI fluctuates greater due to its step response. Accordingly, there are problems in which internal circuits of the LSI 1 and LSI 1a malfunction. If the internal power capacitor C(F) is increased, the fluctuation of the internal voltage will be suppressed even though a production cost will be increased.
The fluctuation of the internal power voltage of the LSI due to the step response means a power supply noise caused by a rapid change of the internal current of the LSI in a transition from a circuit suspend state to a circuit operation state or a transition from the circuit operation state to the circuit suspend state.
As depicted in FIG. 3, it is a feature of the power supply noise in that the internal power voltage of the LSI begins to fluctuate with significantly great amplitude of a resonance period Tres immediately after an operation state of the LSI is transited, and presently converges when the operation state becomes stable. Also, transitions of the operation state are transiting from the circuit suspend state to the circuit operation state and transiting from the circuit operation state to the circuit suspend state.
When the operation enable signals en0 through en3 turn ON while synchronizing with the system clock sclk and the internal power current I starts to flow, the core 0, the core 1, the core 2, the core 3, . . . simultaneously transit from the circuit suspend state to the circuit operation state. In this case, the internal power voltage ivdd begins to greatly fluctuate toward a negative direction. When the circuit operation state becomes stable, the voltage converges presently. As described, when the circuit suspend state transits to the circuit operation state, the internal power voltage ivdd is significantly amplified due to the resonance period Tres.
On the other hand, when the operation enable signals en0 through en3 turn OFF and the internal power current I stops, the core 0, the core 1, the core 2, the core 3, . . . transit from the circuit operation state to the circuit suspend state. The internal power voltage ivdd begins to greatly fluctuate toward a positive direction. Then, when the circuit suspend state becomes stable, the voltage converges presently. As described, when the circuit operation state transits to the circuit suspend state, the internal power voltage ivdd is significantly amplified due to the resonance period Tres with a reversed phase of the case of transiting from the circuit suspend state to the circuit operation state.
The resonance period Tres is mainly determined based on the internal power capacitor C and the inductance L (Ldd+Lcc) for the LSI 1 and LSI 1a and is expressed as follows:Tres=2×π×√{square root over ( )}(L×C)  (1)when π denotes circle ratio.
In a conventional LSI design, in order to prevent a simple switching noise, an approach through shifting an operation timing of each circuit is applied. Moreover, regarding the power supply noise due to the step response as described above, for example, as depicted in FIG. 4, Tim Fischer et al. proposed to detect a noise being occurred and decrease a clock frequency (a) when the power supply noise occurs, in order for the LSI 1 and the LSI 1a to prevent an internal malfunction (for example, see the following reference document 1).
However, since the approach discussed in the conventional technique decreases the clock frequency when the power supply noise occurs, an LSI performance is degraded. Also, in this approach, since a frequency of a circuit operation is modulated, a resonance phenomenon is promoted. There is a risk in that the power supply noise is further amplified. Moreover, since the power supply noise itself due to the step response can not be controlled, it is impossible to suppress the power supply noise (see FIG. 4 of Fischer et al.).